1. Field of the Invention
This invention relates generally to communication systems and more particularly to high frequency latch circuits used therein.
2. Description of Related Art
Communication systems are known to transport large amounts of data between a plurality of end user devices, which, for example, include telephones (i.e., land lines and cellular), facsimile machines, computers, television sets, personal digital assistants, etc. As is known, such communication systems may be local area networks (LANs) and/or wide area networks (WANs) that are stand-alone communication systems or interconnected to other LANs and/or WANs as part of a public switched telephone network (PSTN), packet switched data network (PSDN), integrated service digital network (ISDN), or the Internet. As is further known, communication systems include a plurality of system equipment to facilitate the transporting of data. Such system equipment includes, but is not limited to, routers, switches, bridges, gateways, protocol converters, frame relays, and private branch exchanges.
The transportation of data within communication systems is governed by one or more standards that ensure the integrity of data conveyances and fairness of access for data conveyances. For example, there are a variety of Ethernet standards that govern serial transmissions within a communication system at data rates of 10 megabits-per-second, 100 megabits-per-second, 1 gigabit-per-second and beyond. Synchronous Optical NETwork (SONET), for example, currently provides for up to 10 gigabits-per-second. In accordance with such standards, many system components and end user devices of a communication system transport data via serial transmission paths. Internally, however, the system components and end user devices may process data in a parallel manner. As such, each system component and end user device must receive the serial data and convert the serial data into parallel data without loss of information. After processing the data, the parallel data must be converted back to serial data for transmission without loss of information.
Accurate recovery of information from high-speed serial transmissions typically requires transceiver components that operate at clock speeds equal to or higher than the received serial data rate. Higher clock speeds require oscillator circuits to have gain-bandwidth products to sustain high frequency oscillations while maintaining low phase noise. High phase noise contributes to clock jitter which degrades clock recovery in high-speed circuits. Higher clock speeds limit the usefulness of prior art clock recovery circuits that require precise alignment of signals to recover clock and/or data. Higher data rates require greater bandwidth for a feedback loop of the clock recovery circuits to operate correctly. Some prior art designs are bandwidth limited.
As the demand for data throughput increases, so do the demands on a high-speed serial transceiver. The increased throughput demands are pushing some current integrated circuit manufacturing processes to their operating limits. Integrated circuit processing limits (e.g., device parasitics, trace sizes, propagation delays, device sizes) and integrated circuit (IC) fabrication limits (e.g., IC layout, frequency response of the packaging, frequency response of bonding wires) limit the speed at which the high-speed serial transceiver may operate without excessive jitter performance or phase noise performance.
One solution for high-speed serial transceivers is to use an IC technology that inherently provides for greater speeds. For instance, switching from a Complementary Metal-Oxide Semiconductor (CMOS) process to a silicon germanium or gallium arsenide process would allow integrated circuit transceivers to operate at greater speeds, but at substantially increased manufacturing costs. CMOS is more cost effective and provides easier system integration. Currently, for most commercial-grade applications, including communication systems, such alternate integrated circuit fabrication processes are too cost prohibitive for widespread use.
Modern communication systems, including high data rate communication systems, typically include a plurality of circuit boards that communicate with each other by way of signal traces, bundled data lines, back planes, etc. Accordingly, designers of high data rate communication transceiver devices often have conflicting design goals that relate to the performance of the particular device. For example, there are many different communication protocols specified for data rates that range from 2.48832 gigabits-per-second for OC48, to 9.95 gigabits-per-second for OC192. Other known standards define data rates of 2.5 gigabits-per-second (INFINIBAND) or 3.125 gigabits-per-second (XAUI). For example, one protocol may specify a peak voltage range of 200–400 millivolts, while another standard specifies a mutually exclusive voltage range of 500–700 millivolts. Thus, a designer either cannot satisfy these mutually exclusive requirements (and therefore cannot support multiple protocols) or must design a high data rate transceiver device that can adapt according to the protocol being used for the communications.
Along these lines, programmable logic devices, and more particularly, field programmable gate array (FPGA) circuits are gaining in popularity for providing the required flexibility and adaptable performance, as described above, for those designers that seek to build one device that can operate according to multiple protocols. Thus, while FPGA technology affords a designer an opportunity to develop flexible and configurable hardware circuits, specific designs that achieve the desired operations must still be developed. Accordingly, there is a need for clock and data recovery circuits within a transceiver device that achieves these design objectives. Additionally, traditional clock and data recovery modules typically include latches on the input to sample and hold the incoming data. These latches tend to exhibit high frequency roll off that limits their usefulness in high data rate designs. Furthermore, at high data rates, traditional latches in data recovery circuitry produce a kickback signal that is easily coupled in to phase detection circuitry possibly causing loss of phase information and contributing to inter-symbol interference. There is a need, therefore, for a high frequency latch that overcomes these limitations.